method and equipment for controlling access to adapters in a computing environment

专利摘要:
METHOD, EQUIPMENT, COMPUTER PROGRAM, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING ACCESS TO ADAPTERS IN A COMPUTER ENVIRONMENT Access to an input/output adapter by configuration is controlled. For each requested access to the adapter, checks are made to determine if the configuration is authorized to access the adapter. If not authorized, then access is denied. If it is authorized but access is temporarily blocked, the execution statement is changed to indicate this. If access is allowed, but access must be blocked for another reason (other than temporary blocking), 10 then access is denied.
公开号:BR112012032854B1
申请号:R112012032854-9
申请日:2010-11-08
公开日:2021-05-11
发明作者:Craddock David；Mark Farrell；Thomas Gregg；Beth Glendening；Greiner Dan
申请人:International Business Machines Corporation；
IPC主号:

专利说明:

BACKGROUND OF THE INVENTION
[001] This invention relates, in general, to input/output (I/O) processing and, in particular, to access control for input/output adapters of a computing environment.
[002] Many system architectures use I/O adapter access control for these adapters using central processing unit (CPU) based address translation mechanisms. In such systems, memory-mapped input/output (MMIO) is used, and the hardware knows, based on how the memory is configured, whether an instruction executed by a processor is pointing to real memory or if it is, actually pointing to memory on one of the adapters. The hardware is then able to orient itself accordingly.
[003] Some systems, however, may not use memory-mapped I/O.
[004] US Patent No. 7,617,340, issued November 10, 2009, to Thomas A. Gregg, "I/O Adapter LPAR Isolation with Assigned Memory Space." with Memory Space Assigned), describes a data processing system and a method of isolating a plurality of I/O adapters in the system. The data processing system also comprises a set of processors in communication with the I/O adapters using a PCIe protocol. Each of the I/O adapters has its own ID (identity). In a preferred embodiment the commands issued by the I/O adapters include a defined Requester ID field including one or more Requester IDs of the I/O Adapters. Requester IDs can be used as an input to a CAM that provides an index to TVT to identify a unique and independent system memory space for the I/O adapter.
[005] US Patent No. 7,530,071, issued May 5, 2009, to Billau et al., “Facilitating Access to Input/Output Resources Via an I/O Partition Shared by Multiple Consumer Partitions” Accessing Input/Output Resources Via an I/O Partition Shared by Multiple Consumer Partitions) describes at least one firmware input/output (I/O) partition provided in a partitioned environment to facilitate access to I/O resources S owned by at least one firmware I/O partition, The I/O resources of a firmware I/O partition are shared by one or more different partitions in the environment, referred to as consumer partitions. Consumer partitions use the firmware partition to access I/O resources. Since firmware I/O partitions are responsible for providing access to the I/O resources owned by those partitions, consumer partitions are freed from this task, reducing the complexity and cost in consumer partitions.
[006] US (Patent Application) Publication No. 2009/0240849 A1, published September 24, 2009, by Corneli et al., "System and Method for Distributing Virtual Input/Output Operations Across Multiple Logical Partitions" ( System and Method for Distributing Input/Output Virtual Operations Across Multiple Logical Partitions) describes the Distributed I/O Virtual Tool that replaces the dedicated VIO server LPARs by distributing virtual I/O functions across multiple applications LPARs connected by a high-speed communication channel. Physical I/O devices are distributed across available LPARs. The Distributed I/O Virtual Appliance assigns each I/O request to an appropriate I/O device. The Distributed I/O Virtual Appliance monitors every I/O request and reassigns I/O devices when performance drops on a specific device or when a device is no longer available. BRIEF SUMMARY
[007] According to an aspect of the present invention, access to the I/O adapters is controlled such that only an authorized configuration can access a given I/O adapter (e.g., adapter function). In one example, it is controlled in those computing environments that are not using memory-mapped I/O.
[008] The shortcomings of the prior art are overcome and advantages are achieved by providing a computer program product to control access to adapters in a computing environment. The computer program product includes a computer readable storage media readable by a processing circuit and storage instructions for execution by the processing circuit to perform a method. The method includes, for example, the execution of an instruction including a request for a configuration to access an adapter, the adapter being identified by a function identifier fed with the request, such execution including the use, by the processor, of the function identifier. to get a function table entry for the adapter, a function table entry that includes the information associated with the adapter; verification, based on information in the function table entry, whether configuration access to the adapter is allowed; and allowing access to the adapter in response to the determination that the configuration is allowed access to the adapter.
[009] Methods and systems relating to one or more aspects of the present invention are also described and claimed herein.
[010] Additional features and advantages are achieved through the techniques of the present invention. Other embodiments and other aspects of the invention are described in detail herein and are considered part of the claimed invention. BRIEF SUMMARY OF THE VARIOUS VIEWS OF THE DRAWINGS
[011] One or more aspects of the present invention are particularly clearly highlighted and claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features and advantages of the invention are evident in the following detailed description, taken in conjunction with the accompanying drawings in which:
[012] FIG. 1A depicts an embodiment of a computational environment for incorporating and using one or more aspects of the present invention;
[013] FIG. 1B depicts another embodiment of a computing environment for incorporating and using one or more aspects of the present invention;
[014] FIG. 1C depicts an example of a computational environment in which each adapter function among a plurality of adapter functions has associated with it a function table entry, in accordance with an aspect of the present invention;
[015] FIG. 2A depicts an embodiment of a function table entry used in accordance with an aspect of the present invention;
[016] FIG. 2B depicts an embodiment of a function identifier used to locate a function table entry, in accordance with an aspect of the present invention;
[017] FIG. 3A depicts an example operating system executing a PCI load instruction to access a particular PCI function, in accordance with an aspect of the present invention;
[018] FIG. 3B depicts an example operating system issuing a PCI storage instruction against a particular PCI function, in accordance with an aspect of the present invention;
[019] FIG. 4 depicts an embodiment of logic for controlling access to a particular adapter function by the operating system, in accordance with an aspect of the present invention;
[020] FIG. 5A depicts an embodiment of a Logical Processor Call instruction used in accordance with an aspect of the present invention;
[021] FIG. 5B depicts an embodiment of a request block used by the Call instruction of the Logic Processor of FIG. A, in accordance with one aspect of the present invention;
[022] FIG. 5C depicts an embodiment of a response block provided by the Call instruction of the Logic Processor of FIG. 5A, in accordance with one aspect of the present invention;
[023] FIG. 6 depicts an embodiment of logic for enabling the PCI function, in accordance with an aspect of the present invention;
[024] FIG. 7A depicts an embodiment of the Modify PCI Function Controls instruction used in accordance with an aspect of the present invention;
[025] FIG. 7B depicts an embodiment of a field used by the Modify PCI Function Controls instruction of FIG. 7A, in accordance with one aspect of the present invention;
[026] FIG. 7C depicts an embodiment of another field used by the Modify PCI Function Controls instruction of FIG. 7A, in accordance with one aspect of the present invention;
[027] FIG. 7D depicts an embodiment of the contents of a function information block (FIB) used in accordance with an aspect of the present invention;
[028] FIG. 8 depicts one embodiment of the logic overview of the Modify PCI Function Controls instruction, in accordance with an aspect of the present invention;
[029] FIG. 9A depicts an embodiment of a PCI Load instruction used in accordance with an aspect of the present invention;
[030] FIG. 9B depicts an embodiment of a field used by the Load PCI instruction of FIG. 9A, in accordance with one aspect of the present invention;
[031] FIG. 9C depicts an embodiment of another field used by the Load PCI instruction of FIG. 9A, in accordance with one aspect of the present invention;
[032] FIGs. 10A-10B depict an embodiment of logic for performing a PCI Load operation, in accordance with an aspect of the present invention;
[033] FIG. 11A depicts an embodiment of a PCI Storage instruction used in accordance with an aspect of the present invention;
[034] FIG. 11B depicts an embodiment of a field used by the Storage PCI instruction of FIG. 11A, in accordance with one aspect of the present invention;
[035] FIG. 11C depicts an embodiment of another field used by the Storage PCI instruction of FIG. 11A, in accordance with one aspect of the present invention;
[036] FIGs. 12A-12B depict an embodiment of logic for performing a PCI Storage operation, in accordance with an aspect of the present invention;
[037] FIG. 13A depicts an embodiment of a PCI Storage Block instruction used in accordance with an aspect of the present invention;
[038] FIG. 13B depicts an embodiment of a field used by the PCI Storage Block instruction of FIG. 13A, in accordance with one aspect of the present invention;
[039] FIG. 13C depicts an embodiment of another field used by the PCI Storage Block instruction of FIG. 13A, in accordance with one aspect of the present invention;
[040] FIG. 13D depicts an embodiment of yet another field used by the PCI Storage Block instruction of FIG. 13A, in accordance with one aspect of the present invention;
[041] FIGs. 14A-14B depict an embodiment of logic for performing a PCI Storage Block operation, in accordance with an aspect of the present invention;
[042] FIG. 15 depicts an embodiment of a computer program product incorporating one or more aspects of the present invention;
[043] FIG. 16 depicts an embodiment of a host computer system for incorporating and using one or more aspects of the present invention;
[044] FIG. 17 depicts a further example of a computer system for incorporating and using one or more aspects of the present invention;
[045] FIG. 18 depicts another example of a computer system comprising a computer network for incorporating and using one or more aspects of the present invention;
[046] FIG. 19 depicts an embodiment of various elements of a computer system for incorporating and using one or more aspects of the present invention;
[047] FIG. 20A depicts an embodiment of the computer system execution unit of FIG. 19 to incorporate and use one or more aspects of the present invention;
[048] FIG. 20B depicts an embodiment of the computer system bypass unit of FIG. 19 to incorporate and use one or more aspects of the present invention;
[049] FIG. 20C depicts an embodiment of the loading/storage unit of the computer system of FIG. 19 to incorporate and use one or more aspects of the present invention; and
[050] FIG. 21 depicts an embodiment of an emulated host computer system for incorporating and using one or more aspects of the present invention. DETAILED DESCRIPTION
[051] According to an aspect of the present invention, access to an adapter by a configuration is controlled. In particular, an ability to control access is provided so that only an authorized configuration can access a given adapter, such as an informed adapter function (e.g., a PCI function). The configuration is, for example, an operating system, a processor, a logical partition, an operating system running in a logical partition, a pageable guest in storage mode (e.g., a guest operating system), etc. The term operating system as used in this document includes device drivers.
[052] In an example in z/Architecture®, a pageable guest is run interpretively through the Initial Interpretive Execution (SIE) instruction at level 2 of interpretation. For example, the logical partition hypervisor (LPAR) executes the SIE instruction to start the logical partition in fixed, physical memory. If z/VM® is the operating system on that logical partition, it issues the SIE instruction to run its guest (virtual) machines on its V=V (virtual) storage. So the LPAR hypervisor uses SIE level 1, and the z/VM® hypervisor uses SIE level 2.
[053] Also, as used herein, the term adapter includes any type of adapter (eg, storage adapter, processing adapter, network adapter, cryptographic adapter PCI adapter, other types of input/output adapters, etc. .). In one embodiment, an adapter includes an adapter function. However, in other embodiments, an adapter can include a plurality of adapter functions. One or more aspects of the present invention apply whether the adapter includes an adapter function or a plurality of adapter functions. In one embodiment, if the adapter includes a plurality of adapter functions, then the control capability mentioned herein applies to each adapter function, in accordance with an aspect of the present invention. In the examples presented here, the adapter is used interchangeably with adapter function (e.g., PCI function) unless otherwise noted.
[054] Furthermore, the term firmware, used hereinafter, includes, e.g., the microcode, millicode or macrocode of the processor. It includes, for example, the hardware-level instructions and/or data structures used in implementing higher-level machine code. In one embodiment, it includes, for example, proprietary code that is typically provided as microcode that includes trusted software or microcode specific to the basic hardware and controls operating system access to system hardware.
[055] An embodiment of a computational environment for incorporating or using one or more aspects of the present invention is described with reference to FIG. 1A. In one example, a computing environment 100 is a System z® server provided by International Business Machines Corporation. The z® System is based on z/Architecture® provided by International Business Machines Corporation. Details regarding z/Architecture® are described in an IBM® publication entitled “z/Architecture Principles of Operation”, IBM Publication No. SA22-7832-07, February 2009. IBM®, z® System and z/Architecture® are registered trademarks of International Business Machines Corporation, of Armonk, New York. Other names used herein may be trademarks or product names of International Business Machines Corporation or other companies.
[056] In one example, the computing environment 100 includes one or more central processing units (CPUs) 102 coupled to a system memory 104 (also called main memory) through a memory controller 106. To access system memory 104 , the central processing unit 102 issues a write or read request that includes an address used to access system memory. The address included in the request is typically not usable directly for accessing system memory, and therefore, is translated to an address directly usable for accessing system memory. The address is translated using a translation mechanism (XLATE) 108. For example, the address is translated from a virtual address to a real or absolute address, using, for example, dynamic address translation (DAT).
[057] The request, including the address (translated if necessary), is received by the memory controller 106. In one example, the memory controller 106 is composed of hardware and is used to mediate access to system memory and to maintain the consistency of memory. This mediation is performed for requests received from CPUs 102, as well as requests received from one or more adapters 110. Similar to central processing units, adapters issue requests to system memory 104 to gain access to system memory.
[058] In one example, adapter 110 is a Peripheral Component Interconnect (PCI) or Express Peripheral Component Interconnect (PCIe) adapter that includes one or more PCI functions. The PCI function issues a request that is forwarded to an I/O hub 112 (eg, a PCI hub) by one or more switches (eg, PCIe switches) 114. In one example, the I/O hub is made up of hardware , including one or more state machines, and is coupled to the memory controller 106 via an I/O memory bus 120.
[059] The input/output hub includes, for example, a 116 root complex that receives the request from a switch. The request includes an input/output address that is provided to an address protection and translation unit 118 that accesses the information used for the request. As examples, the request may include an input/output address used to perform a direct memory access (DMA) operation or to request Message Signaled Interrupt (MSI). The address translation and protection unit 118 accesses the information used for the DMA or MSI request. As a particular example, for a DMA operation, information can be obtained to translate the address. The translated address is then forwarded to the memory controller to access system memory.
[060] In one example, the information used for the DMA or MSI request issued by an adapter is taken from a device table entry of a device table located in the I/O hub (eg, in the address translation and protection unit ). The device table entry includes information for the adapter, and each adapter has at least one device table entry associated with it. For example, there is a device table entry by address space assigned to the adapter. For a request issued from an adapter a device table entry is allocated using a requester ID provided in the request.
[061] In a further embodiment of a computational environment, in addition to or instead of one or more CPUS 102, a central processing complex is coupled to the memory controller 106, as shown in FIG. 1B. In this model, a central processing complex 150 includes, for example, one or more partitions or zones 152 (eg, logical partitions LP1 - LPn), one or more central processors (eg, CP1-CPn) 154, and a hypervisor 156 ( eg, a logical partition manager), each described below.
[062] Each logical partition 152 is capable of functioning as a separate system, that is, each logical partition can be independently zeroed, initially loaded with an operating system or a hypervisor (such as z/VM®, provided by International Business Machines Corporation, Armonk, New York), if desired, and operate with different programs. An operating system, a hypervisor, or an application program running on a logical partition appears to have access to a whole, complete system, but only a part of it is available. The combination of hardware and Licensed Internal Code (also called microcode or milcode) prevents a program in one logical partition from interfering with a program in a different logical partition. This allows multiple different logical partitions to operate on a single or multiple physical processor in split-time mode. In this particular example, each logical partition has a resident operating system 158, which can differ for one or more logical partitions. In one embodiment, operating system 158 is the z/OS® or zLinus operating system, offered by International Business Machines Corporation, Armonk, New York. z/OS® and z/VM® are registered trademarks of International Business Machines Corporation, Armonk, New York.
[063] Central processors 154 are physical processor resources that are allocated to logical partitions. For example, a logical partition 152 includes one or more logical processors, each representing the whole of a portion of the physical resource processor 154 allocated to the partition. The fundamental processor resource can either be dedicated to that partition or shared with another partition.
[064] The logical partitions 152 are managed by a hypervisor 156 implemented by firmware running on the processors 154. Both the logical partitions 152 and the hypervisor 156 comprise one or more programs residing in the respective portion of the central storage associated with the central processors. An example of hypervisor 156 is the Processor Resource/Systems Manager (PR/SM) of International Business Machines Corporation, Armonk, New York.
[065] Although, in this example, a central processing complex with logical partitions is described, one or more aspects of the present invention may be incorporated and used in any other processor units, including single processor or multiprocessor processing units that are not partitioned , among others. The central processing complex described here is just an example.
[066] As described above, an adapter can include one or more adapter functions. More details regarding adapter functions are described with reference to FIG. 1C. As shown in FIG. 1C, each adapter function 180 is coupled to an I/O hub 112 through one or more PCI switches 114. The I/O hub is coupled to logical partitions 152 through the memory I/O bus 120. In this example , the memory controller is not shown, but it can be used. Hub I/O can be coupled to logical partitions directly or through a memory controller.
[067] Each adapter function 180 has a function table entry 182 associated with it that includes information relating to its associated adapter function. For example, as shown in FIG. 2A, function table entry 182 has a plurality of fields including, for example:
[068] Zone Number 202: This field includes a value that is used in a logical partition environment to designate a zone or logical partition. The value of this field indicates which zone (e.g., operating system within the zone) has or has access to the adapter function associated with that function table entry.
[069] In a further embodiment, the zone number can be used to identify the configuration regardless of whether it is a logical partition environment. For example, it could be an operating system identifier or an identifier of another configuration.
[070] Guest Identifier 204: This field is used when the system is in paged storage mode to identify a guest who is allowed to access this adapter function;
[071] Status Indicator 206: This provides an indication whether the function table entry itself is valid, whether the function is enabled, and/or whether the function is in an error state, etc.;
[072] Function Type 208: This provides an indication of the type of function of the adapter (e.g., one function per adapter; multiple functions per adapter, etc.);
[073] Requester ID (RID) 210: This is an adapter function identifier and may include, for example, a bus number, device number, and function number. This field is used, for example, for adapter role configuration space accesses.
[074] As shown in FIG. 3A, the adapter function includes storage 300, which has a plurality of address spaces, including, for example: a configuration space (e.g., PCI configuration space for a PCI function); an I/O space (e.g., PCI I/O space); and one or more memory spaces (e.g., PCI memory space).
[075] The configuration space can be accessed by specifying the configuration space in an instruction issued by the configuration to the adapter function. Also specified in the statement are an offset in the configuration space and a function identifier used to locate the appropriate function table entry that includes the RID. The firmware receives the instruction and determines that it is for the configuration space. Therefore, it uses the RID to generate a request to the hub I/O, and the hub I/O creates a request to access the adapter. The adapter's location is based on the RID, and the offset specifies an offset in the adapter's configuration space. For example, offset specifies a record number in configuration space.
[076] Base Address Register (1 to n) 212: There can be one or more base address registers and each is used to indicate the base address of an I/O address space or a memory space within the adapter function. It is used for accesses to the memory space and/or I/O space of the adapter function.
[077] For example, the offset given in an instruction to access the adapter function is added to the value in the base address register associated with the address space designated in the instruction to obtain the address to be used to access the adapter function. The address identifier provided in the instruction identifies the address space in the adapter function to be accessed and the corresponding BAR to be used;
[078] Device Table Index (1 to n) 214 (FIG. 2A): There can be one or more device table indexes, and each index is an index on the device table to locate a device table entry (DTE ). There are one or more device table entries per adapter function, and each entry includes information associated with the adapter function, including information used to process adapter function requests (eg, DMA requests, MSI requests) and information regarding adapter function requests ( eg, PCI instructions). Each device table entry is associated with an address space within the system memory assigned to the adapter function. The information included in the DTE may depend on the operations supported or enabled for the adapter function (described in more detail below); and
[079] Internal Routing Information 216: This information is used to perform adapter-specific routing. It includes, for example, node, processor chip and hub address information.
[080] Function table entry may include more or less information or different information. The information included may depend on the supported or enabled operations for the adapter function (described in more detail below).
[081] To access a particular function table entry for a given adapter function, a function identifier 184 (FIG. 1C) is used. For example, one or more bits of the function identifier are used as an index into the function table to find a specific function table entry. There is a function identifier 184 for each adapter function. In a particular example, the function identifier includes a plurality of parameters. As shown in FIG. 2B, function identifier 184 includes, for example, an activation identifier 252 indicating whether the identifier is activated; a function number 254 that identifies the function (this is a static identifier and can be used to index into the function table); and an instance number 256 specifying the particular instance of this function identifier.
[082] As described above, adapter functions can issue requests such as memory access, interrupt, etc. requests. Also, a configuration can issue requests for an adapter role. In accordance with one aspect of the present invention, these configuration requests are via specific instructions, which access the adapter or modify control parameters associated with the adapter. Examples of instructions include PCI Load, PCI Storage, and Modify PCI Function Controls, to name a few. These instructions are specific to I/O infrastructure architecture (e.g., PCI).
[083] In an example, as shown in FIG. 3A, an operating system running on a CPU 310 issues a load 312 instruction (eg, Load PCI) to access one of the function storage 300 address spaces. There can be multiple adapter functions within a system and only one operating system may be allowed access to a given adapter. When an operating system issues a PCI Load instruction, access restrictions are enforced, for example, by the firmware to ensure that the operating system issuing the instruction is allowed to access the address space within the adapter function.
[084] In another example, the operating system running on CPU 310 issues a storage instruction 314 (e.g., Storage PCI), which also accesses one of the address spaces. There are other adapter instructions that also need to be controlled so that the operating system (or other configuration) accesses only the adapter function assigned to it.
[085] An embodiment of an operating system's access control to an adapter function is described with respect to FIG. 4. Although this example describes operating system access, it can be used for other settings as well.
[086] With reference to FIG. 4, a policy is initially established by the system administrator or customer that associates each PCI function with a particular configuration (eg, a particular operating system, a particular logical partition, etc.) that is allowed to access the adapter function, STEP 400 This policy is, for example, reconfigurable and is kept in a set of I/O configuration data located in safety memory.
[087] At boot time, the firmware (ie, trusted firmware) traverses the I/O infrastructure bus to determine which adapter functions are included (eg connection) in the infrastructure, STEP 402. The firmware will not consider the adapter as part of the infrastructure if the adapter, as identified by its vital product data, is not supported by the platform. During the bus traversal, the firmware performs a certain number of configurations, STEP 403. This configuration includes initializing the PCIe 114 switches with forwarding information (eg, bus numbers and address information) that will allow successful forwarding of packages to and from the adapter functions. At this time, the supported adapters' configuration spaces are also initialized with the BAR information and the respective requestor IDs, consistent with the forwarding information configured on the switches. Subsequently, a function table entry is created for each supported adapter function and that function table entry is populated with some information, STEP 404. For example, the firmware puts the previously configured BAR information and requester ID in function table entry. Based on the policy, a zone number is established in each function table entry that indicates which logical partition, and therefore which operating system, has access to the adapter function corresponding to the function table entry. In another embodiment, in which the computing environment is not logically partitioned, the zone number can be replaced by another indicator, other than the logical partition, that specifies an operating system. Other indicators can also be used for other types of configuration.
[088] Thereafter, the operating system issues a query to determine which adapter functions it has access to (eg, assigned and assignable), STEP 406. In response to that query, the firmware returns a list one or more adapter functions. As an example, the firmware scans the function table looking for all function table entries with a zone number that matches the zone number of the requesting operating system; and returns a list of adapter functions that match the zone numbers. (In another embodiment, a partial list may be returned). For each adapter function included in the list, a function identifier in the list is provided.
[089] At some point, the operating system attempts to access an adapter function (eg, query an adapter function; access a function address space; or set or modify a device table entry for the adapter function; etc. .), by eg an instruction, STEP 408. The operating system specifies in the instruction the function of the adapter it will access via the function identifier. The firmware then uses this function identifier to find the function table entry corresponding to the adapter function, STEP 410. The zone number in the function table entry is compared to the zone number where the operating system resides, QUERY 412. If they do not match, access is then denied (eg, execution of the instruction is prevented), STEP 414. However, if they do match, a further check is made, in an example, whether access should be blocked for a reason different, QUERY 416. For example, the status stored in the function table entry is used to determine if the operating system has issued an instruction that should be blocked while the firmware performs privileged operations that impact the adapter's function, such as recovery, download firmware, etc.
[090] If there is an indication that access should be blocked, a further determination is made to check whether the blocking is temporary, QUERY 418, that is, if the adapter function is only temporarily unavailable as indicated, for example, by status in the function table entry, in which case the instruction can be completed with a busy signal, STEP 420, and can be tried again. If, however, the adapter's function is not only temporarily blocked, then access is denied, STEP 422.
[091] Returning to QUERY 416, if access is not to be blocked, it is then allowed, STEP 424. For example, the instruction is allowed to execute. This completes processing.
[092] In addition to the above, in another example, if it is determined that the zone number in the function table entry matches the operating system zone number, additional validation can be performed to allow direct access by a guest (eg, guest VM) to an adapter that the guest owns. In this example, a check is performed to see if the guest has access to the adapter. For example, the role table entry is checked for guest ID. If stored in the entry, processing continues; if not, the request is denied.
[093] The above access control capability is employed for instructions issued to the adapter function by configuration, such as PCI Load, PCI Storage, PCI Storage Block, Modify PCI Function Controls and various PLC logical processor call instructions used, for example, to query or enable/disable adapter function. In this example, the instructions are PCI instructions, since adapter functions are adapter PCI functions. However, in other examples, other specific I/O architecture instructions can be used depending on the architecture of the adapter functions.
[094] Additional details regarding some of the instructions are described below. To use a PCI function, it must be enabled. For example, the operating system that wants to use a PCI function performs a query to determine the functions eligible for use (based on the I/O configuration), and selects one of those functions to enable. In one model, the function is activated using a PCI function command determined from a Logical Processor Call instruction. One embodiment of that instruction is depicted in FIG. 5A. As shown in one of the examples, a Logical Processor 500 Call instruction includes an opcode 502 indicating that it is a Logical Processor Call instruction; and the indication for a command 504. In one example, that indication is an address of a request block describing the command to be performed. One embodiment of this request block is depicted in FIG. 5B.
[095] As shown in FIG. 5B, in one example, request block 520 includes a number of parameters, such as an extension field 522, indicating the length of the request block; a command field 524 indicating the established PCI command function; a PCI 526 function identifier, which is the indicator to be provided to either enable or disable the function; an operation code 528, which is used to designate either an enabling or disabling operation; and a number of DMA address spaces (DMAAS) 530, which indicates the requested number of address spaces to be associated with the particular PCI function. More, less or different information can be included in other embodiments. For example, in a virtual environment where the instruction is issued by a host of a paged storage mode guest, a guest identity is provided. Other variations are also possible.
[096] In response to the issuance and processing of the Logical Processor Call instruction, a response block is returned and the information included in the response block depends on the operation to be performed. One embodiment of the response block is depicted in FIG. 5C. In one example, response block 550 includes an extension field 552 indicating the length of the response block; a 554 response code indicating the status of the command; and a PCI function identifier 556 that identifies the PCI function. In response to the enable command, the PCI function identifier is a PCI function enabled identifier. In addition, upon completion of the disable operation, the PCI function identifier is a general identifier that can be activated by an enabling function in the future.
[097] One embodiment of the logic for enabling a PCI function is described with reference to FIG. 6. In one example, this logic is initiated in response to issuing an instruction from the Logic Processor Call in which the command is set to the given PCI function command and the opcode is set to the enable function. This logic is executed, for example, by a processor in response to the operating system or an operating system device driver authorized to execute this logic by issuing the instruction. In another embodiment, the logic can be executed without using the Logical Processor Call instruction.
[098] With reference to FIG. 6, a determination is initially made to check whether the identifier provided in the Logical Processor's Call request block is a valid identifier, QUERY 600, that is, whether the identifier points to a valid entry in the function table or is out of range of valid entries (eg, whether the function number part of the identifier designates an installed function). If the identifier is not known then a corresponding response code is provided indicating that the identifier is not recognized STEP 602. However, if the identifier is known then a further query is made to see if the identifier is enabled, QUERY 604. This determination is made by checking the enabled indicator in the PCI function identifier. If the indication is determined to be disabled identifier, a response code indicating this is returned, STEP 606.
[099] However, if the identifier is known and not enabled (ie, valid for activation), a further determination is made to verify that the requested number of address spaces to be assigned to the PCI function is greater than the maximum value. , Query 608. To make this determination, the number of DMA address spaces as specified in the request block is compared to the maximum value (provided, in one example, based on policy). If the number of address spaces is greater than the maximum value, a response code indicating an invalid value for the DMA address spaces is provided, STEP 610. Otherwise, a determination is made to verify the number of spaces address space is available, QUERY 612. This determination is made by checking that there are available entries in the device table for the requested number of address spaces. If the requested number of address spaces is not available then a response code indicating that there are not enough resources is returned, STEP 614. Otherwise, processing continues to enable the PCI function.
[100] The given identifier is used to locate an entry in the function table, STEP 616. For example, one or more designated bits of the identifier are used as an index into the function table to locate a particular function table entry. In response to the location of the appropriate function table entry, a determination is made to verify that the function is enabled, QUERY 618. This determination is made by checking the enable indicator in the function table entry. If the function is already enabled (i.e., the indicator is set to one), a response code is then returned indicating that the PCI function is already in the requested state, STEP 620.
[101] If the function is not yet enabled, then processing continues to check if the function is in a permanent error state, REFER TO 622. If the permanent error state indicator in the function table entry indicates that it is in a state If the function is in a permanent error state, then a response code is returned indicating this, STEP 624. However, if the function is not in a permanent error state, a determination is made to verify that an error recovery has been initiated for the function, Query 626. If the recovery initiated flag in the function table entry is set, then the response code indicating that recovery has started is provided, STEP 628. Otherwise, an additional query is made to see if the PCI function is busy, REFER TO 630. Again, if the busy indicator check in the function table entry indicates that the PCI function is busy, then this indication is given, STEP 632. However, if the PCI function is not in a permanent error state, recovery has not started and is not busy, then one more query is made to see if the operating system is allowed to enable this PCI function, STEP 634.
[102] In one example, the permission check includes validating the zone number in the FTE to that of the operating system issuing the instruction. If they are not the same, then the operating system is not granted permission. If they are equal, then a permission indicator is checked in the role table entry. If there is no permission based on the permission indicator in the role table entry, then a response code indicating an unauthorized action is provided, STEP 636. However, if all tests are successful, a further determination is made for to find out if DTEs are available for this PCI function, REFER TO 638. As an example, determination of DTE availability can be based on DTEs that are not currently enabled on the I/O hub. Additionally, a policy may apply to limit the number of DTEs available for a given operating system or logical partition. Any available DTE that is accessible to the adapter can be assigned. If there are no DTEs available, then a response code is returned indicating that one or more of the requested DTEs are unavailable, STEP 640.
[103] If DTEs are available, then the number of DTEs corresponding to the number of address spaces requested are assigned and activated, STEP 642. In one example, activation includes setting the activation flag on each DTE to be activated. In addition, activation includes, in this model, the installation of content addressable memory (CAM) to provide an index for each DTE. For example, for each DTE, a CAM entry is loaded with the index, and the CAM makes it easy to find a DTE.
[104] In addition, DTEs are associated with the function table entry, STEP 644. This includes, for example, adding each DTE index to the function table entry. The function is then marked as enabled by setting the enable indicator in the function table entry, STEP 646. In addition the enabled bit in the identifier is determined, and the instance number is updated, STEP 648. This enabled identifier is then returned, STEP 650, allowing the use of the PCI adapter. For example, in response to activation of the function, registration for address translations and interrupts can be performed, DMA operations can be performed by the PCI function, and/or load, store and block storage instructions can be issued to the function.
[105] As noted above, after enabling the function, various operating parameters are determined in the DTE and/or FTE via the Modify PCI Function Controls instruction. An example of the Modify PCI Function Controls instruction is described with reference to FIGs. 7A-7D.
[106] With reference to FIG. 7A, a Modify PCI Function Controls 700 instruction includes, for example, an opcode 702 indicating the Modify PCI Function Controls instruction; a first field 704 specifying a location at which various information is included regarding the function of the adapter for which operating parameters are being set; and a second field 706 specifying a location from which a PCI function information block is fetched. The contents of the locations designated by Fields 1 and 2 are described in more detail below.
[107] In one embodiment, Field 1 designates a general record that includes various information. As shown in FIG. 7B, the contents of the register include, for example, a function identifier 710 that identifies the function identifier of the adapter on behalf of which the modify instruction is being performed; an address space 712 designating an address space in system memory associated with the adapter function designated by the function identifier; an operational control 714 that specifies the operation to be performed for the adapter function; and status 716 which provides status regarding the instruction when the instruction completes with a predefined code.
[108] In an example, as shown in FIG. 7C, Field 2 designates a logical address 720 of a PCI function information block (FIB) which includes information relating to an associated adapter function. The function information block is used, in accordance with an aspect of the present invention, to update a device table entry and/or function table entry (or other location) associated with the adapter function. Information is stored in the FIB during adapter initialization and/or configuration, and/or in response to a particular event.
[109] In FIG. 7D more details concerning the function information block are described. In one embodiment, a function information block 750 includes the following fields: Format 751: This field specifies the format of the FIB.
[110] Intercept Control 751: This field is used to indicate whether execution of specific instructions by a guest via guest pageable mode results in instruction interception;
[111] Error Indication 754: This field includes error state indication for adapter and direct memory access interrupts. When the bit is set (e.g., 1), one or more errors were detected during the execution of interrupt direct memory access or adapter for the adapter function;
[112] Load/Storage Block 756: This field indicates whether load/storage operations are blocked;
[113] 758 PCI Function Validation: This field includes an enable control for the adapter function. When the bit is set (e.g., 1), the adapter function is considered to be enabled for I/O operations;
[114] Registered Address Space 760: This field includes a direct memory access enable control for an adapter function. When the field is determined (e.g., 1) direct memory access is enabled;
[115] Page Size 761: This field indicates the size of the page or other memory unit to be accessed by the DMA memory access;
[116] PCI Base Address (PBA) 762: This field is a base address for an address space in system memory assigned to the adapter function. Represents the lowest virtual address that the adapter function is allowed to use for direct memory access for the specified DMA address space;
[117] PCI Address Limit (PAL) 764: This field represents the highest virtual address that the adapter function is allowed to access within the specified address space;
[118] Input/Output Address Translation (IOAT) pointer 766: The input/output address translation pointer designates the first of any translation tables used by the translation of a PCI virtual address, or it may directly designate to designate the absolute address of a storage frame that is the result of the translation;
[119] Interrupt Subclass (ISC) 768: This field includes the interrupt subclass used to present adapter interrupts to the adapter function;
[120] Number of Interrupts (NOI) 770: This field designates the number of distinct interrupt codes accepted by an adapter function. This field also defines the size, in bits, of the adapter interrupt vector bit designated by an adapter interrupt vector bit address and adapter interrupt vector bit offset fields;
[121] Adapter Interrupt Bit Vector Address (AIBV) 772: This field specifies the adapter interrupt bit vector address for the adapter function. This vector is used in interrupt processing;
[122] Adapter Interrupt Bit Vector Offset 774: This field specifies the adapter interrupt bit vector offset for the adapter function;
[123] Adapter Interrupt Summary Bit Address (AISB) 776: This field provides an address designating the adapter interrupt summary bit, which is optionally used in uninterrupted processing;
[124] Adapter Interrupt Summary Bit Offset 778: This field provides the adapter interrupt summary bit offset;
[125] Function Measurement Block Address (FMB) 780: This field provides an address of the function measurement block used to collect measurements relating to the adapter function;
[126] Function Measurement Block Key 782: This field includes an access key to access the function measurement block;
[127] Summary Bit Notification Control 784: This field indicates whether there is a summary vector bit being used;
[128] 786 Instruction Authorization Token: This field is used to determine whether a pageable guest in storage mode (e.g., V=guest V) is authorized to execute PCI instructions without host intervention; and
[129] 787 Address Translation Format: This field indicates a selected format for address translation of the highest level of the translation table to be used in the translation (e.g., segment table, 3rd region, etc.).
[130] Information in the function information block is obtained during configuration, initialization, and/or the occurrence of a particular event.
[131] The function information block designated in the Modify PCI Function Controls instruction is used, in accordance with an aspect of the present invention, to modify a selected device table entry, a function table entry, and/or other controls associated with the adapter function designated in the instruction. Upon modification of the device table entry, function table entry, and/or other firmware controls, certain services are provided for the adapter. These services include, for example, adapter interrupts; address translations; reset error state; return load/storage lock; configure function measurement parameters; and configure intercept control.
[132] One embodiment of the logic associated with the Modify PCI Function Controls instruction is depicted in FIG. 8. In one example, the instruction is issued by an operating system (or other configuration) and executed by the processor (e.g. firmware) running the operating system. In this example, the adapter instruction and functions are PCI-based. However, in other examples, a different adapter architecture and corresponding instructions may be used.
[133] In one example, the operating system provides the following operands for the instruction (e.g., in one or more registers designated by the instruction): the PCI function identifier; the identifier of the DMA address space, the control of the operation; and the address of the function information block.
[134] Referring to FIG. 8, initially, a determination is made as to whether the feature that allows the Modify PCI Function Controls instruction is installed, QUERY 800. This determination can be made, for example, by checking an indicator stored in a control block. If the feature is not installed, an exception condition is provided, STEP 802. Otherwise, a determination is made as to whether the instruction was issued by a pageable guest in storage mode (or another guest), QUERY 804. , the host OS will emulate the operation for that guest, STEP 806.
[135] On the other hand, a determination is made as to whether one or more operands are aligned, QUERY 808. For example, a determination is made as to whether the address of the function information block is on a doubleword boundary. In a template, this is optional. If the operands are not aligned, an exception condition is provided, STEP 810.
[136] Otherwise, a determination is made to verify that the function information block is accessible, QUERY 812. If not, then an exception condition is provided, STEP 814. If not, a determination is made to verify if the identifier given in the operands of the Modify PCI Function Controls instruction is enabled, REF 816. In one example, this determination is made by checking for an enable indicator in the identifier. If the identifier is not enabled then an exception condition is provided, STEP 818.
[137] If the identifier is enabled, then the identifier is used to find an entry in the function table, STEP 820, ie at least part of the identifier is used as an index in the function table to locate the entry in the function table. function corresponding to the function of the adapter for which operating parameters are to be set.
[138] A determination is made as to whether the function table entry was found, QUERY 822. If not, an exception condition is provided, STEP 824. If not, a determination is made as to whether the operating system is authorized, QUERY 826. In one example, this includes validating the zone number in the FTE to that of the operating system issuing the instruction. If they are not the same, then the operating system is not authorized. If they are the same, then an additional determination is made as to whether the configuration issuing the statement is a guest. If so, an exception condition (e.g., a host trap) is provided, STEP 828. This query can be ignored if the configuration is not a guest, or other authorizations can be checked if so designated.
[139] A determination is then made as to whether the function is enabled, QUERY 830. In one example, this determination is made by checking an enable indicator in the function table entry. If not enabled then an exception condition is provided, STEP 832.
[140] If the function is enabled then a determination is made as to whether recovery is active, QUERY 834. If recovery is active as determined by the recovery indicator in the function table entry, then an exception condition is provided , 836. However, if retrieval is not active, a further determination is made as to whether the role is busy, 838. This determination is made by checking the busy indicator in the role table entry. If the function is busy then a busy condition is provided, STEP 840. With the busy condition, the instruction can be repeated rather than dropped.
[141] If the function is not busy, an additional check is made to see if the format of the function's information block is valid, CONSULT 842. For example, the FIB format field is checked to determine if this format is supported by system. If invalid, then an exception condition is given, STEP 844. If the format of the function's information block is valid, then a further determination is made as to whether the operational control specified in the operands of the instruction is valid, QUERY 846, that is, whether the operational control is one of the operational controls specified for this instruction. If invalid, an exception condition is provided, STEP 848. However, if operational control is valid, then processing continues with the specific operational control being determined.
[142] Various operations can be specified including, for example, register/unregister address translations; log/unlog adapter interrupts; configure intercept control; reset error state; return load/storage lock indicator, etc. For each of these operations, the operating parameters relating to the operation are copied from the FIB to the DTE and/or FTE (or other location).
[143] Subsequent to booting, a guest can execute a PCI Load, PCI Storage, and PCI Storage Block instruction, each described below.
[144] Referring initially to FIG. 9A, we depict an embodiment of a PCI Load instruction. As shown, the Load PCI instruction 900 includes, for example, an opcode 902 indicating the Load PCI instruction; a first field 904 specifying the location into which data fetched from an adapter function will be loaded; and a second field 906 specifying the location in which various information relating to the adapter function from which the data is to be loaded is included. The contents of the locations designated by Fields 1 and 2 are described below.
[145] In one example, Field 1 designates a general record and, as depicted in FIG. 9B, the contents 904 of that register include a contiguous range of one or more bytes loaded from the location of the adapter function specified in the instruction. In another example, data is loaded into the rightmost byte positions of the record.
[146] In one embodiment, Field 2 designates a pair of general records that include various information. As shown in FIG. 9C, the contents of the records include, for example:
[147] Enabled Identifier 910: This field is an enabled function identifier of the adapter function from which data is to be loaded;
[148] 912 Address Space: This field identifies the address space within the adapter function from which data is to be loaded;
[149] Offset Within Address Space 914: This field specifies the offset within the address space from which the data is to be loaded;
[150] Extension Field 916: This field specifies the length of the load operation (e.g., the number of bytes to be loaded); and
[151] Status Field 918: This field provides a status code applicable when the instruction completes with a predefined code condition.
[152] In one embodiment, the adapter function's loaded bytes must be contained within an integral boundary in the adapter function's designated PCI address space. When the address space designates a memory address space, the size of the integral limit is, for example, two words. When the address space designates an I/O address space or a configuration address space, the integral boundary size is, for example, one word.
[153] One embodiment of the logic associated with a PCI Load instruction is described with reference to FIGs. 10A-10B. In one example, the instruction is issued by an operating system (or other configuration) and executed by the processor (e.g., firmware) running the operating system. In the examples contained here, the adapter instructions and functions are based on PCI. However, in other examples, a different adapter architecture and corresponding instructions may be used.
[154] To issue the instruction, the operating system provides the following operands for the instruction (eg; in one or more registers designated by the instruction): the PCI function identifier, the PCI address space (PCIAS), the offset in space address range, and the length of data to be loaded. Upon successful completion of the PCI Load Instruction, data is loaded into the location (e.g., register) designated by the instruction.
[155] Referring to FIG. 10A, a determination is initially made to verify that the feature that allows the PCI Load instruction is installed, INQUIRY 1000. This determination is made, for example, by checking a stored indicator such as a control block. If the feature is not installed, an exception condition is provided, STEP 1002. Otherwise, a determination is made to verify that the operands are aligned, CONSULT 1004. For example, if certain operands need to be in pairs of par/ registers odd, a check is made if these requirements are met. If the operands are not aligned, then an exception is provided, STEP 1006. On the other hand, if the feature is installed and the operands are aligned, it is necessary to determine if the identifier provided in the operands of the PCI Load instruction is enabled, CONSULT 1008 In one example, this determination is made by checking an activation indicator in the identifier. If the identifier is not enabled, an exception condition is provided, STEP 1010.
[156] If the identifier is enabled, then it is used to locate a function table entry, STEP 1012. At least part of the identifier is used as an index into the function table to locate the function table entry corresponding to the adapter function from which the data is to be loaded.
[157] A determination is then made as to whether the operating system is authorized, QUERY 1014. In one example, this includes validating the zone number in the FTE to that of the operating system issuing the instruction. If they are not the same, then the operating system is not authorized. If they are the same, then an additional determination is made as to whether the configuration issuing the statement is a guest. If so, an exception condition is provided, STEP 1016. This query can be ignored if the configuration is not a guest, or other authorizations can be checked if so designated.
[158] A determination is then made to verify that the function is enabled, REFERENCE 1018. In one example, this determination is made by checking the enable indicator in the function table entry. If not enabled then an exception condition is provided, STEP 1020.
[159] If the function is enabled, then the address space is checked to see if it is valid, QUERY 1022. For example, the specified address space is an address space designated by the adapter function and suitable for this instruction. If the address space is invalid, then an exception condition is provided, STEP 1024. Otherwise, check whether load/storage is blocked, QUERY 1026. In one example, this determination is made by checking the status indicator in the function table entry. If load/storage is blocked then an exception condition is provided, STEP 1028.
[160] However, if load/storage is not blocked, it is verified that the retrieval is active, QUERY 1030. In one example, this determination is made by checking the retrieval indicator initiated in the function table entry. If recovery is active, then an exception condition is given, STEP 1032. Otherwise, a check is made whether the role is busy, QUERY 1034. This determination is made by checking the busy indicator in the role table entry. If the function is busy, a busy condition is provided, STEP 1036. With the busy condition, the instruction can be repeated rather than dropped.
[161] If the function is not occupied, then a further check is made whether the offset specified in the instruction is valid, QUERY 1038, that is, whether the offset is in combination with the extent of the operation within the base and the extent of the space of addressing as specified in the function table entry. If not, an exception condition is given, STEP 1040. However, if the offset is valid, a check is made if the extension is valid, CONSULT 1042, that is, taking into account the type of address space, the offset within the address space, and the size of the integral limit, the extension is valid. If not, an exception condition is provided, STEP 1044. Otherwise, processing continues with the load instruction. (In one embodiment, the firmware performs the above checks.)
[162] Continuing with FIG. 10B, a check is made by the firmware whether the load is for an adapter function configuration address space, QUERY 1050, that is, based on the adapter function memory configuration, whether the specified address space provided in the instruction is in the configuration space. If so, the firmware performs various processing to deliver the request to a hub coupled with the adapter function; the hub then forwards the request to the role, STEP 1052.
[163] For example, the firmware obtains the requester ID from the function table entry indicated by the function identifier given in the operands of the instruction. In addition, the firmware determines, based on the information in the function table entry (e.g., the internal forwarding information), which hub will receive this request. This means that an environment can have one or more hubs and the firmware determines which hub is attached to the adapter function. It then forwards the request to the hub. The hub generates a configuration read request packet, which goes out over the PCI bus to the adapter function identified by the RID in the function table entry. The configuration read request includes the RID and offset (i.e., data address) that are used to fetch the data, as described below.
[164] Going back to QUERY 1050, if the designated address space is not a configuration space, then the firmware once again performs various processing to provide the request to the hub, STEP 1054. The firmware uses the identifier to select an entry from the function table and from that entry gets information to find the proper hub. It also calculates an address from the data that will be used in the load operation. This address is calculated by adding the starting address BAR (with the BAR associated with the address space identifier given in the instruction) taken from the function table entry to the offset given in the instruction. The data address thus calculated is provided to the hub. The hub then takes the address and includes it in a request packet, such as a DMA read request packet, which passes from the PCI bus to the adapter function.
[165] In response to receiving the request via STEP 1052 or STEP 1054, the adapter function fetches the requested data from the specified location (ie, the data address) and returns that data in response to the request, STEP 1056. The response is routed from the adapter role to the I/O hub. Upon receiving the response, the hub forwards it to the home processor. The initial processor then takes the data from the response packet and loads it into the designated location specified in the instruction (e.g., field 1). The PCI Load operation is then completed with an indication of success (e.g., setting a condition code of zero).
[166] In addition to the load instruction that retrieves data from an adapter function and stores it in a designated location, another instruction that can be executed is the store instruction. The store instruction stores data in a location specified in the adapter function. One embodiment of the PCI Storage instruction is described with reference to FIG. 11A. As shown, a PCI Storage instruction 1100 includes, for example, an operation code 1102 indicating the PCI Storage instruction; a first field 1104 specifying the location that includes the data to be stored in the adapter function; and a second field 1106 specifying the location in which various information is included relating to the adapter function in which the data is to be stored. The contents of the locations designated by Fields 1 and 2 are described below.
[167] In one example, Field 1 designates a general record and, as depicted in FIG. 11B, the contents 1104 of that register include a contiguous range of one or more bytes of data to be stored at the specified adapter function location. In another example, data in the rightmost byte positions of the record is stored.
[168] In one embodiment, Field 2 designates a pair of general records that include various information. As shown in FIG. 11B, the contents of the registers include, for example: Enabled Identifier 1110: This field is an enabled function identifier of the adapter function in which the data is to be stored; 1112 Address Space: This field identifies the address space within the adapter function for which data is to be stored; Offset Within Address Space 1114: This field specifies the offset within the address space for which data is to be stored; Extension Field 1116: This field specifies the extent of the store operation (e.g., the number of bytes to be stored); e Status Field 1118: This field provides a status code applicable when the instruction completes with a predefined code condition.
[169] One embodiment of the logic associated with a PCI Storage instruction is described with reference to FIGs. 12A-12B. In one example, the instruction is issued by an operating system, and executed by the processor (e.g., firmware) running the operating system.
[170] To issue the instruction, the operating system provides the following operands to the instruction (eg, in one or more registers designated by the instruction): the PCI function identifier, the PCI address space (PCIAS), the offset in the space of the PCI addressing, the length of the data to be stored and a pointer to the data to be stored. Upon successful completion of the PCI Storage instruction, data is stored in the location designated by the instruction.
[171] Referring to FIG. 12A, initially, a check is made whether the feature that enables the PCI Storage instruction is installed, Query 1200. This determination is made, for example, by checking a stored indicator, such as a control block. If the feature is not installed, an exception condition is provided, STEP 1202. On the other hand, a check is made if the operands are aligned, QUERY 1204. For example, if certain operands need to be in odd/even register pairs, a check is made if these requirements are met. If the operands are not aligned, then an exception is given, STEP 1206. On the other hand, if the feature is installed and the operands are aligned, it is necessary to determine if the identifier given in the operands of the PCI Storage instruction is enabled, CONSULT 1208 In one example, this determination is made by checking an activation indicator in the identifier. If the identifier is not enabled, an exception condition is provided, STEP 1210.
[172] If the identifier is enabled, then it is used to find a function table entry, STEP 1212. At least part of the identifier is used as an index into the function table to find the function table entry corresponding to the adapter function in which the data is to be stored.
[173] A determination is then made as to whether the operating system is authorized, CONSULT 1214. In one example, this includes validating the zone number in the FTE to that of the operating system issuing the instruction. If they are not the same, then the operating system is not authorized. If they are the same, then an additional determination is made as to whether the configuration issuing the instruction is a guest. If so, an exception condition is provided, STEP 1216. This query can be ignored if the configuration is not a guest, or other authorizations can be checked if so designated.
[174] A determination is then made to verify that the function is enabled, REFERENCE 1218. In one example, this determination is made by checking the enable indicator in the function table entry. If not enabled then an exception condition is provided, STEP 1220.
[175] If the function is enabled, then the address space is checked to see if it is valid, QUERY 1222. For example, the specified address space is an address space designated by the adapter function and suitable for this instruction. If the address space is invalid, then an exception condition is provided, STEP 1224. Otherwise, it checks to see if the load/storage is blocked, REFERENCE 1226. In one example, this determination is made by checking the status indicator in the function table entry. If load/storage is blocked then an exception condition is provided, STEP 1228.
[176] However, in case load/storage is not blocked, it is verified that the retrieval is active, QUERY 1230. In one example, this determination is made by checking the retrieval indicator initiated in the function table entry. If recovery is active, then an exception condition is given, STEP 1232. Otherwise, a check is made whether the role is busy, QUERY 1234. This determination is made by checking the busy indicator in the role table entry. If the function is busy, a busy condition is provided, STEP 1236. With the busy condition, the instruction can be repeated rather than dropped.
[177] If the function is not occupied, then a further check is made whether the offset specified in the instruction is valid, CONSULT 1238, that is, whether the offset is in combination with the operation range within the base and the space range of addressing as specified in the function table entry. If not, an exception condition is given, STEP 1240. However, if the offset is valid, a check is made if the extension is valid, CONSULT 1242, that is, taking into account the type of address space, the offset within the address space, and the size of the integral limit the extent is valid. If not, an exception condition is provided, STEP 1244. Otherwise, processing continues with the store instruction. (In one embodiment, the firmware performs the above checks.)
[178] Continuing with FIG. 12B, a check is made by the firmware whether the storage is for an adapter function configuration address space, QUERY 1250, that is, based on the adapter function memory configuration, whether the specified address space provided in the instruction is the configuration space. If so, the firmware performs various processing to deliver the request to a hub coupled with the adapter function; the hub then forwards the request to the role, STEP 1252.
[179] For example, the firmware obtains the requester ID from the function table entry indicated by the function identifier given in the operands of the instruction. In addition, the firmware determines, based on the information in the function table entry (e.g., the internal forwarding information), which hub will receive this request. This means that an environment can have one or more hubs and the firmware determines which hub is attached to the adapter function. It then forwards the request to the hub. The hub generates a configuration write request packet, which goes out over the PCI bus to the adapter function identified by the RID in the function table entry. The configuration write request includes the RID and offset (i.e., data address) that are used to store the data, as described below.
[180] Going back to QUERY 1250, if the designated address space is not a configuration space, then the firmware once again performs several processes to provide the request to the hub, STEP 1254. The firmware uses the identifier to select an entry from the function table and from that entry gets information to find the proper hub. It also calculates an address from the data that will be used in the store operation. This address is calculated by adding the starting address BAR obtained from the function table entry to the offset given in the instruction. The address data thus calculated is provided to the hub. The hub then takes the address and includes it in a request packet, such as a DMA write request packet, which passes from the PCI bus to the adapter function.
[181] In response to receiving the request via STEP 1252 or STEP 1254, the adapter function stores the requested data at the specified location (ie, the data address), STEP 1256. The PCI Storage operation completes with an indication of success (eg, setting a condition code of zero).
[182] In addition to load and store instructions, which typically load or store the maximum of, e.g., 8 bytes, another instruction that can be executed is the block store instruction. The block storage instruction stores larger blocks of data (e.g., 16, 32, 64, 128, or 256 bytes) in a location specified in the adapter function; block sizes are not necessarily limited to powers of two. In one example, the specified location is in an adapter function memory space (not in I/O or configuration space).
[183] One embodiment of a PCI Storage Block instruction is described with reference to FIG. 13A. As shown, a PCI Storage Block instruction 1300 includes, for example, an opcode 1302 indicating the PCI Storage Block instruction; a first field 1304 specifying the location in which various information relating to the adapter function to which the data is to be stored is included; a second field 1306 specifying the location which includes an offset within the specified address space in which the data is to be stored; and a third field 1308 specifying the location that includes an address in system memory of the data to be stored in the adapter function. The contents of the locations designated in Fields 1, 2 and 3 are described below.
[184] In one configuration, Field 1 designates a general record that includes various information. As shown in FIG. 13B, the contents of the record include, for example: Enabled Identifier 1310: This field is an enabled function identifier of the adapter function in which the data is to be stored; Address Space 1312: This field identifies the address space within the adapter function in which data is to be stored; Extension Field 1314: This field specifies the extent of the store operation (e.g., the number of bytes to be stored); e Status Field 1316: This field provides a status code applicable when the instruction completes with a predefined code condition.
[185] In one example, Field 2 designates a general record, and as depicted in FIG. 13C, the register contents include a value (e.g., 64-bit unsigned integer) that specifies the offset within the specified address space in which the data is to be stored.
[186] In an example, Field 3, as depicted in FIG. 13D, includes a logical address in system memory of the first byte of data 1322 to be stored in the adapter function.
[187] One embodiment of the logic associated with a PCI Storage Block instruction is described with reference to FIGs. 14A-14B. In one example, the instruction is issued by an operating system, and executed by the processor (e.g., firmware) running the operating system.
[188] To issue the instruction, the operating system provides the following operands to the instruction (eg, in one or more registers designated by the instruction): the PCI function identifier, the PCI address space (PCIAS), the offset in the space of the PCI addressing, the length of the data to be stored and a pointer to the data to be stored. The pointing operand can include a register and a marked or unmarked offset. Upon successful completion of the PCI Storage Block instruction, data is stored in the adapter location designated by the instruction.
[189] Referring to FIG. 14A, initially, a check is made whether the feature that allows the PCI Storage Block instruction is installed, Query 1400. This determination is made, for example, by checking a stored indicator, such as a control block. If the feature is not installed, an exception condition is provided, STEP 1402. On the other hand, if the feature is installed, a check is made if the identifier given in the operands of the PCI Storage Block instruction is enabled, CONSULT 1404. In one example, this determination is made by checking an activation indicator in the identifier. If the identifier is not enabled, an exception condition is provided, STEP 1406.
[190] If the identifier is enabled then it is used to locate a function table entry, STEP 1412. At least a part of the identifier is used as an index into the function table to locate the function table entry corresponding to the adapter function in which the data is to be stored. A determination is then made as to whether the operating system is authorized, REFERENCE 1414. In one example, this includes validating the zone number in the FTE to that of the operating system issuing the instruction. If they are not the same, then the operating system is not authorized. If they are the same, then an additional determination is made as to whether the configuration issuing the instruction is a guest. If so, an exception condition is provided, STEP 1416. This query can be ignored if the configuration is not a guest, or other authorizations can be checked if so designated.
[191] A determination is then made to verify that the function is enabled, REFER TO 1418. In one example, this determination is made by checking the enable indicator in the function table entry. If not enabled then an exception condition is provided, STEP 1420.
[192] If the function is enabled, then the address space is checked to see if it is valid, REFER TO 1422. For example, the specified address space is a designated address space of the adapter function and suitable for this instruction (ie, a memory space). If the address space is invalid then an exception condition is provided, STEP 1424. Otherwise, it is verified that the load/storage is blocked, REFERENCE 1426. In another example, this determination is made by checking the indicator of status in the function table entry. If load/storage is blocked then an exception condition is provided, STEP 1428.
[193] However, in case load/storage is not blocked, it is verified that the retrieval is active, QUERY 1430. In one example, this determination is made by checking the retrieval indicator initiated in the function table entry. If recovery is active, then an exception condition is given, STEP 1432. Otherwise, a check is made whether the role is busy, QUERY 1434. This determination is made by checking the busy indicator in the role table entry. If the function is busy, a busy condition is provided, STEP 1436. With the busy condition, the instruction can be repeated rather than dropped.
[194] If the function is not occupied, then a further check is made whether the offset specified in the instruction is valid, QUERY 1438, that is, whether the offset is in combination with the extent of the operation within the base and the extent of the space of addressing as specified in the function table entry. If not, an exception condition is given, STEP 1440. However, if the offset is valid, a check is made to see if the extension is valid, SEE 1442, that is, taking into account the type of address space, the offset within the address space, and the size of the integral limit, the extension is valid. If not, an exception condition is provided, STEP 1444. Otherwise, processing continues with the storage block instruction. (In one embodiment, the firmware performs the above checks.)
[195] Continuing with FIG. 14B, a check is made by the firmware that the location that includes the data to be stored is accessible, QUERY 1450, If not, an exception condition is provided, STEP 1452 If so, then the firmware performs various processing to provide the request to a hub attached to the adapter function; the hub then forwards the request to the role, STEP 1454.
[196] For example, the firmware uses the identifier to select a function table entry and from that entry obtains information to find the proper hub. It also calculates an address from the data that will be used in the block storage operation. This address is calculated by adding the starting address BAR (with the BAR being identified by the address space identifier) obtained from the function table entry to the offset given in the instruction. The address data thus calculated is provided to the hub. In addition, the data referenced by the address given in the instruction is fetched from system memory and provided to the I/O hub. The hub then takes the address and includes it in a request packet, such as a DMA write request packet, which passes from the PCI bus to the adapter function.
[197] In response to receipt of the request, the adapter function stores the requested data at the specified location (ie, the data address), STEP 1456. The PCI Storage Block operation completes with a success indication (eg, establishing a condition code of zero).
[198] The ability to control access by a configuration for a particular adapter function was described in detail above. Each adapter role has a role table entry associated with it and located within the role table entry is an indication of which settings (eg, operating systems, logical partitions, guests, etc.) are allowed to access the adapter role. corresponding to the table entry. This is determined by the policy, which is reconfigurable. The policy is executed by the firmware when the configuration issues instructions for the adapter function. Instruction execution is modified (e.g., by an indication) when the adapter function is under privileged firmware control (e.g., in recovery). Access is prevented while the adapter is undergoing system maintenance or for other designated reasons.
[199] A configuration is granted direct access to the adapter without the need to use separate I/O partitions. Strict isolation between partitions is provided while providing extremely low latency access to adapters. No communication between partitions is required to control access to adapters. Provides control without using page tables for adapter-specific instructions.
[200] In the embodiment described here, the adapters are PCI adapters. PCI, as used in this document, refers to any adapter implemented in accordance with a PCI-based specification as defined by the PCI-SIG Peripheral Component Interconnect Special Interest Group. including, but not restricted to, PCI or PCIe. In a particular example, Express Peripheral Component Interconnect (PCIe) is an interconnect component-level standard that defines a bidirectional communication protocol for transactions between I/O adapters and host systems. PCIe communications are encapsulated in packets conforming to the PCIe standard for transmission on a PCIe bus. Transactions originating from I/O adapters and terminating on host systems are called upbound transactions. Transactions originating from host systems and terminating on I/O adapters are called downbound transactions. The PCIe topology is based on unidirectional point-to-point links arranged in pairs (e.g., an upbound link, a downbound link) to form the PCIe bus. The PCI standard is maintained and published by PCI-SIG.
[201] As will be recognized by those skilled in the art, aspects of the present invention may be embodied as a system, method, or computer program product. Thus, aspects of the present invention may take the form of an all-hardware embodiment, an all-software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects that may be referred to in this document as “circuit”, “module” or “system”. Furthermore, aspects of the present invention may be in the form of a computer program product incorporated in one or more computer readable media, with computer readable program code incorporated therein.
[202] Any combination of one or more computer readable media can be used. Computer readable media can be storage media. Computer readable storage media may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, apparatus or device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer readable storage media include: electrical connection having one or more cables, portable computer floppy disk, hard disk, random access memory (RAM), read-only memory (ROM) , erasable programmable read-only memory (EPROM or Flash memory), fiber optics, portable compact disk read-only memory (CD-ROM), optical storage device, or any suitable combination of the foregoing. In the context of this document, computer readable storage media may be any tangible media that contains or stores a program for use by or in connection with an instruction execution system, apparatus or device.
[203] Referring now to FIG. 15, in one example, a computer program product 1500 includes one or more computer readable storage media 1502 for storing computer readable program code media or logic 1504 to provide and facilitate one or more aspects of the present invention.
[204] Program code embedded in computer-readable media may be transmitted using an appropriate medium, including, without limitation, wireless, wired, fiber optic cable, RF, etc., or any combination thereof.
[205] Computer program code to perform operations for aspects of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language, assembler or similar programming languages. Program code may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, and partially on a remote computer, or entirely on a remote computer or server. In the last scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (eg, via the Internet using an Internet Service Provider).
[206] Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products in accordance with embodiments of the invention. It is understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams can be implemented by computer program instructions. Computer program instructions may be provided to a general purpose computer processor, special purpose computer, or other programmable data processing device to produce a machine such that the instructions, executed via the computer's processor or other programmable data processing device, create means to implement the functions/actions specified in the flowchart and/or block or block diagram. Such computer program instructions may also be stored on computer readable media which can direct the computer, other programmable data processing systems, or other devices to function in a particular way, such that the instructions stored on the computer readout produce an article of manufacture including instructions that implement the function/action specified in the flowchart and/or block or block diagram.
[207] Computer program instructions may also be loaded into a computer, other programmable data processing systems, or other devices to perform a series of operational steps to be performed on the computer, other programmable data processing systems, or other devices for producing a process implemented on the computer such that instructions executed on the computer or other programmable data processing systems provide processes for implementing the functions/actions specified in the flowchart and/or block or block diagram.
[208] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of computer systems, methods, and computer program products in accordance with various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or piece of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative embodiments, the functions observed in the block may occur outside the order indicated in the figures. For example, two blocks shown in succession might actually be played more concurrently, or the blocks might sometimes be played in reverse order, depending on the functionality involved. It should also be noted that each block illustration of block diagrams and/or flowcharts, as well as combinations of blocks in the illustration of block diagrams and/or flowcharts, can be implemented by hardware-based special-purpose systems that perform the specified functions or actions, or combinations of special-purpose hardware and computer instructions.
[209] In addition to the above, one or more aspects of the present invention may be provided, offered, distributed, managed, provided, etc., by a service provider that offers management of customer environments. For example, the service provider may create, maintain, support, etc., computer code and/or a computational infrastructure that performs one or more aspects of the present invention for one or more customers. In return, the service provider may be paid by the customer through a subscription and/or a contracted fee, for example. In addition, or alternatively, the service provider may be paid by selling advertising content to third parties.
[210] In one aspect of the present invention, an application may be provided to carry out one or more aspects of the present invention. As an example, the provision of an application comprises the provision of operable computational infrastructure to carry out one or more aspects of the present invention.
[211] As a further aspect of the present invention, a computational framework comprising the integration of a computer readable code into a computer system may be provided, in which the code in combination with the computer system is capable of executing one or more aspects of the present invention.
[212] As yet another aspect of the present invention, a process for integrating the computational infrastructure comprising the integration of computer readable code with a computer system can be provided. The computer system encompasses a computer readable media, in which the computer media comprises one or more aspects of the present invention. The code in combination with the computer system is capable of carrying out one or more aspects of the present invention.
[213] Furthermore, more, less, or different information may be included in function table entries, device table entries, and/or function identifier that do not originate from the scope of the present invention. Furthermore, although tables are described, any data structure can be used and the term table should include all of these data structures. Furthermore, other instructions may be controlled by one or more aspects of the present invention. Many other variations are possible.
[214] In addition, other types of computing environments can benefit from one or more aspects of the present invention. As an example, a data processing system suitable for storing and/or executing program code can be used that includes at least two processors coupled directly or indirectly to memory elements via a system bus. Memory elements include, for example, local memory employed during the actual execution of program code, mass storage, and cache memory that provides temporary storage of at least some program code in order to reduce the number of times the code has to be retrieved from mass storage at runtime.
[215] Input/Output or I/O Devices (including, but not limited to, keyboards, displays, pointing devices, DASD-direct access storage devices, tapes, CDs, DVDs, flash drives and other memory media, etc.) can be coupled to the system either directly or with the intervention of I/O controllers. Network adapters can also be attached to the system to allow data processing to couple with other data processing systems or with remote printers or storage devices through the intervention of public or private networks. Modems, cable modems and Ethernet cards are just some of the available types of network adapters.
[216] With reference to FIG. 16, representative components of a Host Computer system 5000 for implementing one or more aspects of the present invention are depicted. The host computer representative 5000 comprises one or more 5001 CPUs in communication with computer memory (ie, central storage) 5002, as well as I/O interfaces for storing 5011 media devices and 5010 networks for communicating with other computers or networks storage area (SAN) and the like. The 5001 CPU supports an architecture that has architected instruction configuration and architected functionality. The CPU 5001 can have dynamic address translation (DAT) 5003 for transforming program addresses (virtual addresses) into real memory addresses. A DAT typically includes a lookaside translation buffer (TLB) 5007 to save translations so that the last accesses to the memory blocks of computer 5002 do not need address translation delay. Typically, a 5009 cache is employed between the 5002 computer memory and the 5001 processor. The 5009 cache can have a large hierarchical cache available for more than one CPU and smaller, faster caches (lower levels) between the larger cache and each CPU. In some implementations, lower-level caches are split to provide low-level caches for instruction fetching and data accesses. In one embodiment, an instruction is fetched from memory 5002 by a fetch instruction unit 5004 via a cache 5009. The instruction is decoded in an instruction decoding unit 5006 and sent (with other instructions in some embodiments) to the unit or units. of instruction execution unit 5008. Typically, several execution units 5008 are used, for example, arithmetic execution unit, floating point execution unit and branch instruction execution unit. The instruction is executed by the execution unit, accessing operands from the specified instruction registers or from memory as needed. If an operand needs to be accessed (loaded or stored) from memory 5002, a load/store unit 5005 typically indicates access under control of the instruction being executed. Instructions can be executed in hardware circuits or in internal microcode (firmware) or by a combination of both.
[217] As noted, a computer system includes information in local (or primary) storage, as well as addressing, protection, and reference and alteration recording. Some aspects of addressing include the format of addresses, the concept of address spaces, the various types of addresses, and the way in which one type of address is translated into another type of address. Some of the primary storages include permanently assigned storage locations. Primary storage provides the system with fast-access, directly addressable data storage. Both data and programs must be loaded onto primary storage (from input devices) before they can be processed.
[218] Primary storage can include one or more smaller, faster access buffer stores, sometimes called caches. A cache is generally physically associated with a CPU or I/O processor. The effects, other than performance, of physical construction and usage of different storage media are generally not observable by the program.
[219] Separate caches can be maintained for instructions and for data operands. Information within a cache is held in contiguous bytes on an integral boundary called a cache block or cache line (or line for short). A template can provide a CACHE EXTRACTION ATTRIBUTE instruction that returns the cache line size in bytes. A template can also provide PREFET DATA and RELATIVELY LONG PREFET DATA instructions that prefetch storage to the data or instruction cache or flush data from the cache.
[220] Storage is viewed as a long horizontal string of bits. For most operations, storage accesses proceed in a left-to-right sequence. The bit string is subdivided into eight-bit units. The eight-bit unit is called byte, which is the basic building block of all information formats. Each byte location in storage is identified by a unique non-negative integer, which is the address of that byte's location, or simply the byte address. Adjacent byte locations have consecutive addresses, starting with a left 0 and continuing in sequence from left to right. Addresses are unsigned binary integers and are either 24, 31, or 64 bits.
[221] Information is transmitted between storage and the CPU or a channel subsystem one byte, or a group of bytes, at a time. Unless otherwise specified, for example, on z/Architecture®, a group of bytes in storage is addressed by the leftmost byte of the group. The number of bytes in the group is either implicitly or explicitly specified by the operation to be performed. When used in a CPU operation, a group of bytes is called a field. Within each group of bytes, for example in z/Architecture®, bits are numbered in a sequence from left to right. In z/Architecture®, the leftmost bits are sometimes called the “higher order” bits and the rightmost bits are the “lower order” bits. Bit numbers, however, are not storage addresses. Only bytes can be addressed. To operate with individual bits of a byte in storage, the byte is accessed in its entirety. Bits in a byte are numbered from 0 to 7, left to right (e.g., in z/Architecture®). Bits in an address can be numbered 8-31 or 40-63 for 24 bit addresses, or 1-31 or 33-63 for 31 bit addresses; they are numbered 0-63 for 64 bit addresses. Within any other multi-byte fixed length format, the bits that make up the format are numbered consecutively starting at 0. For error detection purposes, and preferably for correction, one or more check bits may be transmitted with each byte or with a group of bytes. Such check bits are automatically generated by the machine and cannot be directly controlled by the program. Storage capacities are expressed in number of bytes. When the length of a storage operand field is suggested by the opcode of an instruction, the field is said to have a fixed length, which can be one, two, four, eight, or sixteen bytes. Larger fields can be suggested by some instructions. When the length of a storage operand field is not suggested but explicitly stated, the field is said to have a variable length. Variable length operands can vary in length by one-byte increments (or with some instructions, in two-byte multiples or other multiples). When information is put into storage, only the contents of these byte locations are replaced and included in the designated field, even though the physical path width for storage may be greater than the length of the field being stored.
[222] Certain units of information must be in full-range storage. An integral range for an information unit is called when its storage address is a multiple of the unit's length in bytes. Special names were given to the 2, 4, 8 and 16 byte fields in full range. Half-word is a group of two consecutive bytes in a two-byte range and is the basic instruction building block. Word is a group of four consecutive bytes in a four-byte range. A double word is a group of eight consecutive bytes in an eight-byte range. A quad word is a group of 16 consecutive bytes in a 16-byte range. When storage addresses designate half words, words, double words and quad words, the binary representation of the address contains one, two, three or four rightmost zero bits, respectively. Instructions must be in 2-byte integral boundaries. The storage operands of most instructions do not have boundary alignment requirements.
[223] In devices that implement separate caches for instructions and data operands, a significant delay can be experienced if the program stores in a cache line from which instructions are subsequently fetched, regardless of whether the storage alters the instructions fetched subsequently.
[224] In one embodiment, the invention may be carried out by software (sometimes referred to as licensed internal code, firmware, microcode, millicode, picocode, and the like, any of which are consistent with the present invention). Referring to FIG. 16, software program code embodying the present invention is typically accessed by processor 5001 of host system 5000 from long-term storage media devices 5011, such as CD-ROM drive, tape disk, or hard disk. . The software program code can be embodied on any of the variety of media known for data processing systems, such as floppy disk, hard disk or CD-ROM. Code may be distributed on such media, or may be distributed to users from computer memory 5002 or storage of one computer system on a network 5010 to other computer systems for use by users of those other systems.
[225] Software program code includes an operating system that controls the function and interaction of various computer components and one or more application programs. Program code is normally paged from a storage media device 5011 to computer storage of relatively higher speed 5002 where it is available for processing by processor 5001. Techniques and methods for realizing software program code in memory , in the physical media and/or in the distribution software code via networks are well known and will not be discussed further in this document. Program code, when created and stored on tangible media (including, but not limited to, electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like), is always referred to as a “computer program product”. The computer program product media is typically readable by a processor circuit, preferably in a computer system for execution by the processor circuit.
[226] FIG. 17 illustrates the representation of a workstation or server hardware system where the present invention can be performed. System 5020 of FIG. 17 comprises a representative base computer system 5021, such as a personal computer, a workstation or a server, including optional peripheral devices. Base computer system 5021 includes one or more processors 5026 and a bus employed to connect and enable communication between processor(s) 5026 and the other components of system 5021 in accordance with known techniques. The bus connects the 5026 processor to 5025 memory and 5027 long-term storage which can include a hard disk (including any magnetic media, CD, DVD and flash memory, for example) or a tape drive. System 5021 may also include a user interface adapter, which connects microprocessor 5026 over the bus to one or more interface devices, such as keyboard 5024, mouse 5023, printer/scanner 5030, and/or other interface devices, which may be any user interface device such as touch screen, digitized input platform, etc. The bus also connects a 5022 video device, such as an LCD screen or monitor, to the microprocessor through a video adapter.
[227] The 5021 system can communicate with other computers or computer networks through a network adapter capable of communicating 5028 with a 5029 network. Examples of network adapters are communication channels, “token ring” protocol, Ethernet or modems. Alternatively, the 5021 system can communicate using a wireless interface such as a CDPD (Digital and Cellular Data Packet) card. System 5021 may be associated with other computers in a local area network (LAN) or a wide area network (WAN), or system 5021 may be a client in a client/server arrangement with another computer, etc. All of these configurations, as well as the appropriate communication hardware and software, are known to experts.
[228] FIG. 18 illustrates a data processing network 5040 in which the present invention may be used. Data processing network 5040 may include a plurality of individual networks, such as a wireless network and a wired network, each of which may include a plurality of individual workstations 5041, 5042, 5043, 5044. you may note, one or more LANs may be included, and each LAN may comprise a plurality of intelligent workstations coupled to a host processor.
[229] Still referring to FIG. 18, networks may also include mainframe computers or servers such as an intermediary computer (client server 5046) or application server (remote server 5048 that can access a data repository and can also be accessed directly from a workstation 5045). An intermediary computer 5046 serves as an entry point into each individual network. The intermediate machine (gateway) is required when connecting one network protocol to another. Intermediate machine 5046 can be preferably coupled to another network (eg Internet 5047) via a communication link. Intermediate machine 5046 may also be directly coupled to one or more workstations 5041, 5042, 5043, 5044 using a communication link. The intermediary computer can be deployed using a System z® IBM eServer™ server provided by the International Business Machines Corporation.
[230] Referring at the same time to FIG. 17 and FIG. 18, software programming code embodying the present invention is accessible by processor 5026 of system 5020 from long-term storage media 5027, such as a CD-ROM drive or a hard disk. The software program code can be embodied on any of the variety of media known for data processing systems, such as floppy disk, hard disk or CD-ROM. Code may be distributed on such media, or may be distributed to users 5050, 5051 from the memory or storage of one computer system on a network to other computer systems for use by users of those other systems.
[231] Alternatively, the programming code can be embedded in memory 5025, and accessed by processor 5026 using the processor bus. This programming code includes an operating system that controls the function and interaction of various computer components and or more 5032 application programs. The program code is normally paged from storage media 5027 to high-speed memory 5025 where it is available for processing by the 5026 processor. The techniques and methods for embedding software programming code in memory, on physical media, and/or software distribution code over networks are well known and will not be discussed further in this document. Program code, when created and stored on tangible media (including, but not limited to, electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like), is always referred to as a “computer program product”. The computer program product media is typically readable by a processor circuit, preferably in a computer system for execution by the processor circuit.
[232] The cache that is most readily available to the processor (usually faster and smaller than other caches on the processor) is the lowest cache (L1 or tier 1) and the primary storage (main memory) is the tier cache highest (L3 if there are 3 levels). The lowest level cache is often divided into instruction cache (I-Cache) storing machine instructions to be executed and data cache (D-Cache) storing data operands.
[233] Referring to FIG. 19, an exemplary processor embodiment is depicted for processor 5026. Typically one or more levels of cache 5053 are employed to buffer memory blocks in order to improve processor performance. The 5053 cache is high-speed buffering cache lines of usable memory data. Typical cache lines are 64, 128, or 256 bytes of memory data. Separate caches are often used more to store instructions than to store data. Cache coherence (synchronization of in-memory row copies and caches) is often provided by various snooping algorithms well known in the art. Cache is typically referred to as the storage of the 5025 main memory of a processor system. On a processor system that has 4 tiers of 5053 cache, the 5025 primary storage is sometimes called the tier 5 (L5) cache, as it is generally faster and stores only a portion of the nonvolatile storage (DASD - Storage Device). Direct Access, tape, etc.) which is available on the computer system. Primary storage 5025 stores pages of data paged in and out of primary storage 5025 by the operating system.
[234] A program counter (instruction counter) 5061 keeps track of the address of the current instruction being executed. A program counter on a z/Architecture® processor is 64 bits and can be cut to 31 or 24 bits to support previous addressing limits. The program counter is typically embedded in a computer's PSW (program status word) so that it continues during context switching. Thus, a running program, having a program counter value, can be stopped, for example, by the operating system (switching from program environment context to operating system environment). The program PSW maintains the program counter value while the program is not active, and the program counter (in PSW) of the operating system is used while the operating program is running. Typically, the program counter is incremented by a value equal to the number of bytes in the current instruction. RISC (simplified) instructions are typically of fixed length while CISC (complex) instructions are typically of variable length. IBM z/Architecture® instructions are CISC instructions with a length of 2, 4, or 6 bytes. Program counter 5061 is modified either by a context switching operation or by a branch taken operation of a branch instruction, for example. In a toggle operation context, the current program counter value is saved in the program status word along with other status information about the program being executed (such as condition codes), and a new program counter value is loaded pointing to an instruction of a new program module to be executed. A branch taken operation is performed to allow the program to make decisions or loops within the program by loading the result of the branch instruction into program counter 5061.
[235] Typically, an instruction fetch unit 5055 is employed to fetch instructions on behalf of the processor 5026. The fetch unit brings either "the next instructions in the sequence", destination instructions of the taken branch instructions, or the first instructions of a program following the context switch. Modern instruction fetching units often use prefetch techniques to speculate prefetch instructions based on the similarity that the prefetched instructions might be used. For example, a fetch unit can fetch 16 bytes of instruction that includes the next sequential instruction and additional bytes of later sequential instructions.
[236] The fetched instructions are then executed by the processor 5026. In one embodiment, the fetched instructions are passed to a dispatch unit 5056 of the fetching unit. The dispatch unit decodes the instruction(s) and forwards information about them to the appropriate units 5057, 5058, 5060. An execution unit 5057 will typically receive information about decoded arithmetic instructions from the instruction fetch unit 5055 and will perform arithmetic operations on operands according to the instruction's opcode. The operands are provided to the execution unit 5057 preferably either from memory 5025, from the architected registers 5059 or from an immediate field of the instruction being executed. Execution results, when stored, are stored either in memory 5025, registers 5059 or other machine hardware (such as control register, PSW registers and the like).
[237] A 5026 processor typically has one or more units 5057, 5058, 5060 to perform the instruction's function. Referring to FIG. 20A, execution unit 5057 can communicate with general architected registers 5059, decode/dispatch unit 5056, load storage unit 5060, and other 5065 processor units through logic interface 5071. Execution unit 5057 can employ several register circuits 5067, 5068, 5069 to store information that the Arithmetic and Logical Unit (ALU) 5066 will work on. The ALU performs arithmetic operations such as addition, subtraction, multiplication, and division, as well as logic functions such as and, or and unique-or (XOR), rotation, and mobility. The ALU preferably supports specialized operations that are dependent on design. Other circuits may provide other 5072 features, including condition codes and software recovery, for example. Typically, the result of an ALU operation is stored in an output register circuit 5070 which can forward the result to a variety of other processing functions. There are various arrangements of processor units, the present description is only intended to provide an understandable representation of an embodiment.
[238] An ADD (sum) instruction, for example, would be executed in a 5057 execution unit that has arithmetic and logic functionality, while a floating-point instruction, for example, would be executed in a floating-point unit with specialized point capability. floating. Preferably, the execution unit operates on operands identified by an instruction by performing an opcode function defined in the operands. For example, an ADD instruction can be executed by execution unit 5057 on operands found in two registers 5059 identified by the instruction register fields.
[239] Execution unit 5057 performs arithmetic addition of two operands and stores the result in a third operand, where the third operand can be a third register or one of the two source registers. The execution unit preferably uses a Logical and Arithmetic Unit (ALU) 5066 that is capable of performing a variety of logic functions, such as Mobility, Rotation, And, Or, and XOR, as well as a variety of algebraic functions, including addition , subtraction, multiplication, division. Some 5066 ALUs are designed for scalar operations and some for floating point. Data can be Big Endian (where the least significant byte is at the highest byte address) or Little Endian (where the least significant byte is at the lowest byte address) depending on the architecture. IBM's z/Architecture® is Big Endian. Signed fields can be in sign-magnitude, 1's complement, or 2's complement form, depending on the architecture. A 2's complement number is advantageous in that the ALU does not need to draw a subtraction capability, since a negative or positive value in the 2's complement only requires addition within the ALU. Numbers are commonly described in shorthand (shorthand format), where a 12-bit field defines an address of a 4096 byte block and is generally described as a 4 Kbyte (Kilobyte) block, for example.
[240] Referring to FIG. 20B, the branch instruction information for executing a branch instruction is typically sent to a branch unit 5058 which often employs a branch prediction algorithm, such as a branch history table 5082 to predict the outcome of the branch. before the completion of other conditional operations. The target of the current branch instruction will be fetched and executed speculatively before completion of conditional operations. When conditional operations are completed, the speculatively executed branch instructions will also be completed or discarded based on the conditions of the conditional operation and the speculated result. A typical branch instruction might test condition codes and branch to a destination address if the condition codes match the branch instruction branch requirement, a destination address can be calculated based on various numbers including those found in the fields record or in an immediate field of the instruction, for example. Bypass unit 5058 can utilize an ALU 5074 that has a plurality of input register circuits 5075, 5076, 5077 and an output register circuit 5080. Bypass unit 5058 can communicate with general registers 5059, dispatch unit -decoding 5056 or other circuits 5073, for example.
[241] The execution of a group of instructions can be interrupted for a variety of reasons, including a context switch initiated by an operating system, an exception or a program error causing the context switch, an I/ S causing a context switch or multithreaded activity of a plurality of programs (in a multithreaded environment), for example. Preferably, a context-switching action saves state information about a currently running program and then loads state information about another program being called. Status information can be saved in hardware registers or in memory, for example. The status information preferably comprises a program counter value pointing to the next instruction to be executed, condition codes, memory translation information and architected register contents. Context switching activity can be performed on hardware circuits, application programs, operating system programs, or firmware code (microcode, picocode, or licensed internal code (LIC)) alone or in combination.
[242] The processor accesses operands according to defined instruction methods. The instruction can provide an immediate operand using the value of a part of the instruction, it can provide one or more register fields explicitly pointing to either general purpose registers or special purpose registers (floating point registers, for example). The instruction may use implicit registers identified as operands by an opcode field. The instruction can use memory locations for operands. The memory location for an operand can be provided by a register, an immediate field, or a combination of registers and immediate field, as exemplified by the z/Architecture® long shift feature where the instruction defines a base register, a register index and an immediate field (offset field) that are added together to provide the address of the operand in memory, for example. The location mentioned here typically implies a location in main memory (primary storage) unless otherwise noted.
[243] With reference to FIG. 20C, a processor accesses storage using a load/storage unit 5060. Load/storage unit 5060 can perform a load operation by obtaining the address of the target operand in memory 5053 and loading the operand into register 5059 or another location of memory 5053, or may perform a store operation by obtaining the address of the destination operand in memory 5053 and storing the data obtained from a register 5059 or other memory location 5053 in the location of the destination operand in memory 5053. load/storage 5060 can be speculative and may access memory in a sequence that is out of order with respect to the instruction sequence, however, load/storage unit 5060 must maintain appearance for programs whose instructions are executed in order. The 5060 load/storage unit can communicate with general registers 5059, decode/dispatch unit 5056, cache/memory interface 5053 or other 5083 elements and comprises various register circuits, ALUs 5085 and control logic 5090 to calculate the addresses of storage and provide pipeline sequencing to keep operations in order. Some operations may be out of order, but the load/storage unit provides the functionality to make out of order operations appear in the program as being performed in order, as is well known to experts.
[244] Preferably, addresses that an application program “see” are often called virtual addresses. Virtual addresses are sometimes called "logical addresses" and "effective addresses". These virtual addresses are virtual in that they are redirected to physical memory locations by one or a variety of dynamic address translation (DAT) technologies, including, without limitation, simply prefixing a virtual address with an offset value. , translate the virtual address by means of one or more translation tables, which translation tables preferably comprise at least one segment table and one page table alone or in combination, preferably the segment table having an entry pointing to the page table. In z/Architecture®, a translation hierarchy is provided including a region first table, region second table, region third table, segment table, and optional page table. Address translation performance is often improved by utilizing a lookaside translation buffer (TLB) that comprises entries mapping a virtual address to an associated physical memory location. Entries are created when the DAT translates a virtual address using the translation tables. Subsequent use of the virtual address can then use the fast TLB entry instead of the slow sequential translation table accesses. TLB content can be managed by a variety of replacement algorithms including LRU (Least Recently Used).
[245] In the case where the processor belongs to a multiprocessor system, each processor has responsibility for keeping shared resources, such as I/O, caches, TLBs and memory, built in for coherence. Typically, snooping technologies will be used to maintain cache coherency. In a snooping environment, each cache line can be marked as being in any shared state, exclusive state, modified state, invalid state and the like in order to facilitate sharing.
[246] The 5054 I/O units (FIG. 19) provide the processor with the means to attach itself to peripheral devices including tape, disk, printers, videos, and workstations, for example. I/O units are often introduced to the computer program by software drivers. On mainframes, such as IBM's z® System, channel adapters and open system adapters are mainframe I/O units that provide communications between the operating system and peripheral devices.
[247] In addition, other types of computing environments can benefit from one or more aspects of the present invention. As an example, an environment may include an emulator (eg, software or other emulation mechanisms), in which a particular architecture (including, for example, execution instruction, architected functions such as address translation, and architected records) or a subset of it is emulated (eg, on a native computer system with processor and memory). In such an environment, one or more emulation functions of the emulator can implement one or more aspects of the present invention, even if the computer running the emulation has a different architecture than the capabilities being emulated. As an example, in emulation mode, the specific instruction or operation being emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.
[248] In an emulation environment, a host computer includes, for example, memory to store instructions and data, instruction fetch unit to fetch instructions from memory and to optionally provide local hold for the fetched instruction; instruction decoding unit for receiving the fetched instruction and for determining the type of instructions that have been fetched; and instruction execution unit for executing the instructions. Execution may include loading data into a memory register; storing the data back in memory from a record; or performing some sort of logical or arithmetic operation, as determined by the decoding unit. In one example, each unit is implemented in software. For example, the operations being performed by the units are implemented as one or more subroutines within the emulator software.
[249] More particularly, on a mainframe, machine-architected instructions are used by programmers, usually "C" programmers today, often through a compiler application. These instructions stored on storage media can be executed originally on an IBM z/Architecture® Server, or alternatively on machines running other architectures. They can be emulated on existing or future IBM® mainframe servers and other IBM® machines (e.g., Power Systems and System x® servers). They can run on machines running Linux on a wide variety of machines using hardware manufactured by IBM®, Intel®, AMD™, and others. In addition to running on this hardware on z/Architecture®, Linux can be used as well as machines that use emulation by TurboHercules (www.turbohercules.com/), Hercules (www.hercules-390.org/) or FSI (Fundamental Software, Inc.) (www.funsoft.com/), where execution is usually in emulation mode. In emulation mode, emulation software is run by a native processor to emulate the architecture of an emulated processor.
[250] The native processor typically runs emulation software comprising either firmware or native operating system to perform emulation of the emulated processor. The emulation software is responsible for fetching and executing instructions from the emulated processor architecture. Emulation software maintains an emulated program counter to keep track of instruction boundaries. Emulation software can fetch one or more emulated machine instructions at a time and convert them to a corresponding group of source machine instructions for execution by the source processor. These converted instructions can be stored so that faster conversion can be achieved. However, the emulation software must maintain the architecture rules of the emulated processor architecture in order to ensure the correct operation of operating systems and applications written for the emulated processor. In addition, the emulation software shall provide features identified by the emulated processor architecture, including, without limitation, control registers, general purpose registers, floating point registers, dynamic address translation function including segment tables and address tables. page, for example, interrupt mechanisms, context switching mechanisms, TOD clocks, and interfaces architected to I/O subsystems so that an operating system or application program designed to run on the emulated processor can run on the source processor that owns the emulation software.
[251] A specific instruction being emulated is decoded, and a subroutine is called to perform the function of the individual instruction. An emulation software function emulating a function of an emulated processor is implemented, for example, in a subroutine or a "C" driver, or some other method of providing a driver for the specific hardware, as may be done by experts, after understanding the description of the preferred embodiment. Various software and hardware emulation patents including, but not limited to, US Patent No. 5,551,013, entitled "Multiprocessor for Hardware Emulation'" by Beausoleil et al.; and US Patent No. 6,009,261, entitled "Preprocessing of Stored Target Routines for Emulating Incompatible Instructions on a Target Processor" by Scalzi et al; and US Patent No. 5,574,873 entitled "Decoding Guest Instruction on Directly Access Emulation Routines that Emulate the Guest Instructions" by Davidian et al; and US Patent No. 6,308,255 entitled "Symmetrical Multiprocessing Bus and Chipset Used for Coprocessor Support Allowing Non-Native Code to Run in a System". Non-Native Code Runs on a System), by Gorishek et al; and US Patent No. 6,463,582 entitled "Dynamic Optimizing Object Code Translator for Architecture Emulation and Dynamic Optimizing Object Code Translation Method." of Object Optimization), by Lethin et al; and US Patent No. 5,790,825, entitled "Method for Emulating Guest Instructions on a Host Computer Through Dynamic Recompilation of Host Instructions" (Method for Emulating Guest Instructions on a Computer Host through Dynamic Recompilation of Host Instructions), by Eric Traut; and many others, available to experts, illustrate a variety of known ways to achieve emulation of an architected instruction format for a machine other than a target machine.
[252] In FIG. 21, we have an example of a 5092 emulated host computer system that emulates a 5000’ host computer system of a host architecture. In the emulated host computer system 5092, the host processor (CPU) 5091 is an emulated host processor (or virtual host processor) and comprises a host processor 5093 that has a different source instruction set architecture than the host computer processor 5091 5000 '. Emulated host computer system 5092 has memory 5094 accessible to emulation processor 5093. In the exemplified embodiment, memory 5094 is partitioned into a portion of host computer memory 5096 and a portion of emulation routines 5097. 5096 is available for host computer programs emulated 5092 according to host computer architecture. The emulation processor 5093 executes source instructions from a set of instructions architected of an architecture different from that of the emulated processor 5091, the source instructions being obtained from the memory of emulation routines 5097, and can access a host instruction for execution from within. a program in host computer memory 5096 using one or more instructions obtained in a sequence &access/decode routine that can decode the host instructions accessed to determine a source instruction execution routine for emulating the function of the host instruction accessed. Other features that are defined for the 5000' host computer system architecture can be emulated by architected resource routines, including features such as general purpose registers, control registers, dynamic address translation, and I/O subsystem support and caching. processing, as an example. Emulation routines can also take advantage of functions available in the 5093 emulation processor (such as general registers and dynamic virtual address translation) to improve the performance of the emulation routines. Special hardware and load reduction machines can also be provided to assist the 5093 processor in emulating the 5000’ host computer function.
[253] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this document, the forms “a”, “an” and “o”, “a” also include the plural forms, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and/or "comprising", when used in this specification, determine the presence of certain features, integers, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, component elements and/or groups of them.
[254] The structures, materials, actions and equivalents in all ways or steps plus the corresponding function elements in the claims below, if any, are intended to include any structure, material or action for the performance of the function in combination with other elements claimed as per specifically claimed. The description of the present invention is being presented for the purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiment was chosen and described in order to better explain the principles of the invention and practical applications, and to enable others skilled in the art to grasp the invention for various embodiments with various modifications as suitable for the particular use contemplated.

权利要求:
Claims (10)
[0001]
1. EQUIPMENT FOR CONTROLLING ACCESS TO ADAPTERS IN A COMPUTING ENVIRONMENT, characterized by: memory (104); processor (102) in communication with the memory (104), where the equipment (100) is configured to carry out a method comprising the execution, by a processor (102) coupled to an adapter (110), of an instruction, such an instruction comprising a request made by a configuration to access the adapter (110), the adapter (110) being identified by a function identifier (184) provided with the request, and the execution comprising using the function identifier (184) to selecting from a function table a particular function table entry for the adapter (110) specified by the function identifier (184), said function table entry being stored in the memory (104) associated with the processor (102) including information for determine if the configuration has permission to access the adapter (110); and determining, through the processor (102), based on information from the function table entry, whether the configuration is allowed access to the adapter (110), where the determination comprises comparing one or more configuration attributes requesting access to the adapter ( 110) for one or more selected attributes of the function table entry to determine if the configuration is allowed to access the adapter (110), and to allow access to the adapter (110), based on the determination that the configuration is allowed to access the adapter (110).
[0002]
2. EQUIPMENT FOR CONTROLLING ACCESS TO ADAPTERS IN A COMPUTING ENVIRONMENT, according to claim 1, characterized in that: the determination comprises the comparison of a zone number (202) in the function table entry (182) with the zone number of the configuration, where the configuration is allowed access upon the comparison response indicating equality.
[0003]
3. EQUIPMENT FOR ACCESS CONTROL TO ADAPTERS IN A COMPUTER ENVIRONMENT, according to claim 1, characterized in that: the configuration comprises a guest, and the determination comprises the verification in the function table entry of a guest identifier (204), where the guest has access permission, in response to the identifier being in the role table entry.
[0004]
4. EQUIPMENT FOR CONTROLLING ACCESS TO ADAPTERS IN A COMPUTING ENVIRONMENT, according to claim 1, characterized in that: the method further comprises determining whether access should be blocked for one or more reasons other than verification of permission, such determination using the status information of the function table entry 182, where access is allowed in response to the determination that it should not be blocked.
[0005]
5. EQUIPMENT FOR ACCESS CONTROL TO ADAPTERS IN A COMPUTATIONAL ENVIRONMENT, according to claim 4, characterized in that: it is determined that the access must be blocked, and the mentioned method also comprises decision on whether the access must be blocked temporarily; and providing a busy indicator for the configuration upon determining that access should be temporarily blocked.
[0006]
6. EQUIPMENT FOR ACCESS CONTROL TO ADAPTERS IN A COMPUTING ENVIRONMENT, according to claim 1, characterized in that: the method further comprises determining a plurality of adapters (110) available for the computing environment; creating a function table entry (182) for each adapter (110) of the plurality of adapters (110); determining which adapters (110) out of the plurality of adapters (110) are accessible to the configuration; and indicating in the function table entry of each adapter (110) that it is accessible to configuration information relating to the configuration.
[0007]
7. EQUIPMENT FOR ACCESS CONTROL TO ADAPTERS IN A COMPUTING ENVIRONMENT, according to claim 1, characterized in that: The instruction is based on the adapter architecture (110).
[0008]
8. METHOD FOR CONTROLLING ADAPTER ACCESS IN A COMPUTING ENVIRONMENT characterized by the steps of: execution, by a processor (102) coupled to an adapter (110), of an instruction, such instruction comprising a request made by a configuration to access the adapter (110), the adapter (110) being identified by a function identifier (184) provided with the request, and the execution comprising using the function identifier (184) to select a particular function table entry from a function table. for the adapter (110) specified by the function identifier (184), said function table entry being stored in memory (104) associated with the processor (102) including information to determine whether the configuration is allowed to access the adapter (110) ; and determining, through the processor (102), based on information from the function table entry, whether the configuration is allowed access to the adapter (110), where the determination comprises comparing one or more configuration attributes requesting access to the adapter ( 110) for one or more selected attributes of the function table entry to determine if the configuration is allowed to access the adapter (110), and to allow access to the adapter (110), based on the determination that the configuration is allowed to access the adapter (110).
[0009]
9. METHOD FOR CONTROLLING ACCESS TO ADAPTERS IN A COMPUTATIONAL ENVIRONMENT, according to claim 8, characterized in that: the determination comprises the comparison of a zone number (202) in the function table entry (182) with the zone number of the configuration, where the configuration is allowed access upon the comparison response indicating equality.
[0010]
10. METHOD FOR CONTROLLING ACCESS TO ADAPTERS IN A COMPUTATIONAL ENVIRONMENT, according to claim 8, characterized by: determination to know whether access should be blocked for one or more reasons other than verification of permission, such determination using state information of the function table entry, where access is allowed in response to the determination that it should not be blocked.

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2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

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2021-03-30| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2021-05-11| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 11/05/2021, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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US12/821,184|US8626970B2|2010-06-23|2010-06-23|Controlling access by a configuration to an adapter function|

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US12/821,184|2010-06-23|

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PCT/EP2010/067041|WO2011160720A1|2010-06-23|2010-11-08|Controlling access by a configuration to an adapter function|

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